Development and test of a mini-Data Acquisition system for the High-Luminosity LHC upgrade of the ATLAS Monitored Drift Tube detector

New front-end electronics including ASICs and FPGA boards are under development for the ATLAS Monitored Drift Tube (MDT) detector to handle the large data rates and harsh environment expected at high-luminosity LHC runs. A mobile Data Acquisition (miniDAQ) system is designed to perform integration tests of these front-end electronics. In addition, it will be used for surface commissioning of 96 small-radius MDT (sMDT) chambers and for integration and commissioning of new front-end electronics on the present ATLAS MDT chambers. Details of the miniDAQ hardware and firmware are described in this article. The miniDAQ system is also used to read out new front-end electronics on an sMDT prototype chamber using cosmic muons and results obtained are shown.Comment: 10 pages, 12 figure

Evaluation of commercial ADC radiation tolerance for accelerator experiments

Electronic components used in high energy physics experiments are subjected to a radiation background composed of high energy hadrons, mesons and photons. These particles can induce permanent and transient effects that affect the normal device operation. Ionizing dose and displacement damage can cause chronic damage which disable the device permanently. Transient effects or single event effects are in general recoverable with time intervals that depend on the nature of the failure. The magnitude of these effects is technology dependent with feature size being one of the key parameters. Analog to digital converters are components that are frequently used in detector front end electronics, generally placed as close as possible to the sensing elements to maximize signal fidelity. We report on radiation effects tests conducted on 17 commercially available analog to digital converters and extensive single event effect measurements on specific twelve and fourteen bit ADCs that presented high tolerance to ionizing dose. Mitigation strategies for single event effects (SEE) are discussed for their use in the large hadron collider environment.Comment: 16 pages, 8 figure

Development of COTS ADC SEE Test System for the ATLAS LAr Calorimeter Upgrade

Radiation-tolerant, high speed, high density and low power commercial off-the-shelf (COTS) analog-to-digital converters (ADCs) are planned to be used in the upgrade to the Liquid Argon (LAr) calorimeter front end (FE) trigger readout electronics. Total ionization dose (TID) and single event effect (SEE) are two important radiation effects which need to be characterized on COTS ADCs. In our initial TID test, Texas Instruments (TI) ADS5272 was identified to be the top performer after screening a total 17 COTS ADCs from different manufacturers with dynamic range and sampling rate meeting the requirements of the FE electronics. Another interesting feature of ADS5272 is its 6.5 clock cycles latency, which is the shortest among the 17 candidates. Based on the TID performance, we have designed a SEE evaluation system for ADS5272, which allows us to further assess its radiation tolerance. In this paper, we present a detailed design of ADS5272 SEE evaluation system and show the effectiveness of this system while evaluating ADS5272 SEE characteristics in multiple irradiation tests. According to TID and SEE test results, ADS5272 was chosen to be implemented in the full-size LAr Trigger Digitizer Board (LTDB) demonstrator, which will be installed on ATLAS calorimeter during the 2014 Long Shutdown 1 (LS1).Comment: 8 pages, 14 figure

FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.Comment: 8 pages, 8 figures, accepted by IEEE - Transactions on Nuclear Scienc

Development of High-Speed, Low-fixed Latency Serial Links for the Router of ATLAS NSW sTGC Detector

The ATLAS experiment at the Large Hadron Collider (LHC) needs to be upgraded in order to cope with the increased luminosity and particle rates expected for the High Luminosity LHC (HL­LHC) running. Part of the phase­1 upgrade, to be done in the 2018/19 shutdown, is the replacement of the present muon forward detector (wheel) by a new detector, the so called New Small Wheel (NSW). The NSW detector consists of two detector technologies and the work here is on the small­strip Thin­Gap Chambers (sTGC). For sTGC, it requires very high­speed electronic triggering of signal events. The data must be quickly digitized, serialized, and transmitted off­detector for computer processing. The serialized data is sent to the trigger processor through a routing system that serves as a switchyard for all active signals. Design requirements on the router are low latency and stable/predictable data transfer timing with high­speed serial links (4.8 Gbps). We describe a 4.8 Gbps (maximum 6.6 Gbps) serial link structure based on GTP transceivers embedded in Xilinx Artix­7 FPGA that uses an adapted cut­through switching method in the FPGA fabric logic to deal with the latency issue. A flexible routing algorithm developed to minimize signal loss will be discussed. The implementation of the whole process firmware and the latency test results achieved with this serial link system are presented and discussed

Upgrade of the ATLAS Muon Drift Tube FE Electronics for HL-LHC Runs

The ATLAS monitored drift tube (MDT) chambers are the main component of the precision tracking system in the ATLAS muon spectrometer. The MDT system is capable of measuring the sagitta of muon tracks to an accuracy of 60 μm, which corresponds to a momentum accuracy of about 10% at pT=1 TeV. To cope with large amount of data and high event rate expected from the High-Luminosity LHC (HL-LHC) upgrade, ATLAS plans to use the MDT detector at the first-trigger level to improve the muon transverse momentum resolution and reduce the trigger rate. The new MDT trigger and readout system will have an output event rate of 1 MHz and a latency of 6 us at the first-level trigger. A new trigger and readout system has been proposed. Prototypes for two frontend ASICs and a data transmission board have been designed and tested, and detailed simulation of the trigger latency has been performed. We will present the overall design of the trigger and readout system and focus on latest results from different ASIC and board prototypes and system integration